The present invention relates generally to integrated circuits, and more particularly, to testing flip-flop circuitry for state retention.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital and sometimes analog components on a single chip. ICs may have manufacturing defects such as physical failures and fabrication defects that cause the ICs to malfunction. Thus, the ICs need to be tested to detect manufacturing defects. Design for test (DFT) techniques add testability features to ICs that allow automatic test equipment (ATEs) to execute various fault tests using test patterns generated by an automatic test pattern generator (ATPG) on the ICs to identify manufacturing defects. ICs undergoing testing are referred to as circuits-under-test (CUT).
ICs that undergo fault testing include multiple scan flip-flops that form a scan-chain. Test data is shifted in one end of the scan chain and out the other with the starting data compared to the shift out data to detect any faults. A particular type of flip-flops known as a state retention power gating (SRPG) flip-flops are used to store the state of an integrated circuit during power-down. It is desirable to have the capability to test the functionality of the SRPG flip-flops during the manufacturing process and while in use in the field.